A threshold logic gate based on clocked coupled inverters
暂无分享,去创建一个
[1] Kenneth J. Breeding. Digital Design Fundamentals , 1989 .
[2] Kai-Yeung Siu,et al. On Optimal Depth Threshold Circuits for Multiplication and Related Problems , 1994, SIAM J. Discret. Math..
[3] A. Gago,et al. New types of digital comparators , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.
[4] Robert J. Francis,et al. Ganged CMOS: trading standby power for speed , 1990 .
[5] Chung Len Lee,et al. Bit-sliced median filter design based on majority gate , 1992 .
[6] Jehoshua Bruck,et al. Depth efficient neural networks for division and related problems , 1993, IEEE Trans. Inf. Theory.
[7] Thomas Kailath,et al. Toward Massively Parallel Design of Multipliers , 1995, J. Parallel Distributed Comput..
[8] Maria J. Avedillo,et al. Low-power CMOS threshold-logic gate , 1995 .
[9] Richard E. Ladner,et al. The Complexity of Computing Symmetric Functions Using Threshold Circuits , 1992, Theor. Comput. Sci..
[10] Wentai Liu,et al. Precise final state determination of mismatched CMOS latches , 1995, IEEE J. Solid State Circuits.