A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation
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William J. Dally | Stephen G. Tell | Mahmut E. Sinangil | Brian Zimmer | Thomas H. Greer | John W. Poulton | C. Thomas Gray | C. T. Gray | Matthew R. Fojtik | Jesse Wang | Andreas J. Gotterba | Jason Golbus | W. Dally | J. Golbus | B. Zimmer | J. Poulton | Matthew R. Fojtik | S. Tell | M. Sinangil | Jesse Wang
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