Low power and low voltage CMOS digital circuit techniques
暂无分享,去创建一个
[1] H. Oguey,et al. CODYMOS frequency dividers achieve low power consumption and high frequency , 1973 .
[2] Kazuo Yano,et al. A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic , 1990 .
[3] Anantha P. Chandrakasan,et al. Low-power CMOS digital design , 1992 .
[4] Christer Svensson,et al. Trading speed for low power by choice of supply and threshold voltages , 1993 .
[5] Richard T. Witek,et al. A 160 MHz 32 b 0.5 W CMOS RISC microprocessor , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
[6] Christer Svensson,et al. Low Power Circuit Techniques , 1996 .
[7] Wolfgang Fichtner,et al. Low-power logic styles: CMOS versus pass-transistor logic , 1997, IEEE J. Solid State Circuits.
[8] Wolfgang Nebel,et al. Low power design in deep submicron electronics , 1997 .
[9] Christer Svensson,et al. New single-clock CMOS latches and flipflops with improved speed and power savings , 1997 .
[10] Atila Alvandpour,et al. Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).
[11] Per Larsson-Edefors,et al. Impact of Miller Capacitance on Power Consumption , 1998 .