Polysilicon gate with depletion-or-metallic gate with buried channel: what evil worse ?

Metallic gates are expected to overcome polysilicon's limitations, such as polydepletion. Nevertheless, this option must be associated with buried channel to ensure low V/sub TH/ operation. Taking into account realistic projections on technological capabilities, such as active gate doping, oxide thickness or junction depth, we confirm that the degradation in performances due to the buried channel is definitively much more restrictive than that relative to the polydepletion.

[1]  M. Mendicino,et al.  PVD TiN metal gate MOSFETs on bulk silicon and fully depleted silicon-on-insulator (FDSOI) substrates for deep sub-quarter micron CMOS technology , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[2]  T. Sugii,et al.  Realization of 0.1 /spl mu/m buried-channel PMOSFETs by device restructuring using tilted well implantation technology , 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

[3]  C. Hu,et al.  Observation of reduced boron penetration and gate depletion for poly-Si/sub 0.8/Ge/sub 0.2/ gated PMOS devices , 1999 .

[4]  Chenming Hu,et al.  Gate engineering for deep-submicron CMOS transistors , 1998 .

[5]  Y.V. Ponomarev,et al.  Gate polysilicon optimization for deep-submicron MOSFETs , 1999, 29th European Solid-State Device Research Conference.

[6]  D. Frank,et al.  25 nm CMOS design considerations , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).