Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis

One of the major reliability concerns in nanoscale very large-scale integration design is the time-dependent negative- bias-temperature-instability (NBTI) degradation. Due to the higher operating temperature and increasing vertical oxide field, threshold voltage (Vt) of PMOS transistors can increase with time under NBTI. In this paper, we examine the impact of NBTI degradation in memory elements of digital circuits, focusing on the conventional 6T-SRAM-array topology. An analytical expression for the time-dependent Vt degradation in PMOS transistors based on the empirical reaction-diffusion (RD) framework was employed for our analysis. Using the RD-based Vt model, we analytically examine the impact of NBTI degradation in critical performance parameters of SRAM array. These parameters include the following: (1) static noise margin; (2) statistical READ and WRITE stability; (3) parametric yield; and (4) standby leakage current (IDDQ). We show that due to NBTI, READ stability of SRAM cell degrades, while write stability and standby leakage improve with time. Furthermore, by carefully examining the degradation in leakage current due to NBTI, it is possible to characterize and predict the lifetime behavior of NBTI degradation in real circuit operation.

[1]  H. Reisinger,et al.  Analysis of NBTI Degradation- and Recovery-Behavior Based on Ultra Fast VT-Measurements , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

[2]  C.H. Kim,et al.  An Analytical Model for Negative Bias Temperature Instability , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[3]  P. Nicollian,et al.  Material dependence of hydrogen diffusion: implications for NBTI degradation , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[4]  B.C. Paul,et al.  Impact of NBTI on the temporal performance degradation of digital circuits , 2005, IEEE Electron Device Letters.

[5]  Kaushik Roy,et al.  Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point sampling , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[6]  D. Kwong,et al.  Dynamic NBTI of PMOS transistors and its impact on device lifetime , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[7]  Kaushik Roy,et al.  Statistical design and optimization of SRAM cell for yield enhancement , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[8]  Y. Yeo,et al.  Characterization and Physical Origin of Fast Vth Transient in NBTI of pMOSFETs with SiON Dielectric , 2006, 2006 International Electron Devices Meeting.

[9]  K. Jeppson,et al.  Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices , 1977 .

[10]  Yung-Huei Lee,et al.  Effect of pMOST bias-temperature instability on circuit reliability performance , 2003, IEEE International Electron Devices Meeting 2003.

[11]  K. Ahmed,et al.  On the Physical Mechanism of NBTI in Silicon Oxynitride p-MOSFETs: Can Differences in Insulator Processing Conditions Resolve the Interface Trap Generation versus Hole Trapping Controversy? , 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

[12]  S. Demuynck,et al.  AC NBTI studied in the 1 Hz -- 2 GHz range on dedicated on-chip CMOS circuits , 2006, 2006 International Electron Devices Meeting.

[13]  D. Kwong,et al.  Fast DNBTI components in p-MOSFET with SiON dielectric , 2005, IEEE Electron Device Letters.

[14]  Thomas A. DeMassa,et al.  Digital Integrated Circuits , 1985, 1985 IEEE GaAs IC Symposium Technical Digest.

[15]  E. Seevinck,et al.  Static-noise margin analysis of MOS SRAM cells , 1987 .

[16]  Sachin S. Sapatnekar,et al.  Impact of NBTI on SRAM read stability and design for reliability , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[17]  Jin-Fu Li,et al.  Built-in redundancy analysis for memory yield improvement , 2003, IEEE Trans. Reliab..

[18]  R. Rajsuman,et al.  Iddq testing for CMOS VLSI , 1994, Proceedings of the IEEE.

[19]  P. Nicollian,et al.  Negative bias temperature instability mechanism: The role of molecular hydrogen , 2006 .

[20]  Yu Cao,et al.  Modeling and minimization of PMOS NBTI effect for robust nanometer design , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[21]  F. Nouri,et al.  On the dispersive versus arrhenius temperature activation of nbti time evolution in plasma nitrided gate oxides: measurements, theory, and implications , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[22]  W. Abadeer,et al.  Behavior of NBTI under AC dynamic circuit conditions , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[23]  M.A. Alam,et al.  A methodology for accurate assessment of soft-broken gate oxide leakage and the reliability of VLSI circuits , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[24]  V. Reddy,et al.  A comprehensive framework for predictive modeling of negative bias temperature instability , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[25]  J. Meindl,et al.  The impact of intrinsic device fluctuations on CMOS SRAM cell stability , 2001, IEEE J. Solid State Circuits.

[26]  D. Schroder,et al.  Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing , 2003 .

[27]  S. Mahapatra,et al.  Gate Leakage vs. NBTI in Plasma Nitrided Oxides: Characterization, Physical Principles, and Optimization , 2006, 2006 International Electron Devices Meeting.

[28]  M.A. Alam,et al.  A critical examination of the mechanics of dynamic NBTI for PMOSFETs , 2003, IEEE International Electron Devices Meeting 2003.

[29]  K. Yamaguchi,et al.  The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling , 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

[30]  M. Alam,et al.  Critical analysis of short-term negative bias temperature instability measurements : Explaining the effect of time-zero delay for on-the-fly measurements , 2007 .