A scalable quantitative measure of IR-drop effects for scan pattern generation

Analysis of power grid IR-drop during scan test application has drawn growing attention because excessive IR-drop may cause a functionally correct device to fail at-speed testing. The analysis is challenging since the power grid IR-drop profile depends on not only the switching cells locations but also the power grid structure. This paper presents a scalable implementation methodology for quantifying the IR-drop effects of a set of switching cells. An example of its application to guide power-safe scan pattern generation is illustrated. The scalability and effectiveness of the proposed quantitative measure is evaluated with a 130 nm industrial design with 800 K cells.

[1]  Qiang Xu,et al.  Layout-aware pseudo-functional testing for critical paths considering power supply noise effects , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[2]  Mark Mohammad Tehranipoor,et al.  Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical Paths , 2009, 2009 27th IEEE VLSI Test Symposium.

[3]  Xiaoqing Wen,et al.  CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing , 2009, 2009 Asian Test Symposium.

[4]  Rohit Kapur,et al.  Bounded Adjacent Fill for Low Capture Power Scan Testing , 2008, 26th IEEE VLSI Test Symposium (vts 2008).

[5]  Kwang-Ting Cheng,et al.  Analysis of performance impact caused by power supply noise in deep submicron devices , 1999, DAC '99.

[6]  Wu-Tung Cheng,et al.  Improved weight assignment for logic switching activity during at-speed test pattern generation , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

[7]  Irith Pomeranz,et al.  Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs , 2006, 2006 IEEE International Test Conference.

[8]  Masanori Hashimoto,et al.  Gate delay estimation in STA under dynamic power supply noise , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

[9]  I. Duff A survey of sparse matrix research , 1977, Proceedings of the IEEE.