论文信息 - A novel fabrication process of surface via-holes for GaAs power FETs

A novel fabrication process of surface via-holes for GaAs power FETs

A simple new fabrication process of via-holes has been developed for GaAs power FETs. This process features deep trench etching from the wafer surface followed by refilling the trench by conformal electro-plating. The Surface Via-Hole (SVH) is engraved by extremely high rate ECR etching. We obtained the etching rate of over 4 /spl mu/m/min with a completely anisotropic smooth profile. The conformal metal deposition around the trench is achieved by pulse-modulated electro-plating. The GaAs power FET with SVH showed better linearity than the conventional wire-bonded one. The present SVH process is applicable to almost all the GaAs FETs or MMICs with very small area consumption and suitable for the high volume production.

[1] R. Pucel,et al. Modeling via hole grounds in microstrip , 1991, IEEE Microwave and Guided Wave Letters.

[2] L. G. Hipwood,et al. Dry etching of through substrate via holes for GaAs MMIC’s , 1985 .

[3] A. Geissberger,et al. Application of plasma etching to via hole fabrication in thick GaAs substrates , 1985 .

[4] K. Hilton,et al. Via holes for GaAs MMICs fabricated using reactive ion etching , 1985 .

[5] C. B. Cooper,et al. Dry etching of via connections for GaAs monolithic microwave integrated circuits fabrication , 1987 .

[6] Daisuke Ueda,et al. Low-voltage operation GaAs spike-gate power FET with high power-added efficiency , 1997 .

[7] H. R. Kim,et al. Via hole process for GaAs monolithic microwave integrated circuit using two‐step dry etching , 1993 .

[8] High power-added efficiency and low distortion GaAs power FET employing spike-gate structure , 1997 .

[9] F. Ren,et al. Dry processed, through‐wafer via holes for GaAs power devices , 1993 .