A systems approach for quality and reliability of chip scale package assembly

This paper reviews many factors that affect interconnect reliability of commercial-off-the-shelf (COTS) chip scale package (CSP) assemblies. These include: package type, package build, board design, and assembly variables. Methods of accelerated environmental testing were discussed and reasons for unrealistic life projections for CSP assembly reliability by numerous modelers is also examined. Preliminary thermal cycling test results in the range of -30/spl deg/C to 100/spl deg/C for test vehicles, especially a double sided assembly were also presented. It was concluded that availability of meaningful assembly reliability test results are needed to accelerate implementation of this technology. The JPL-led CSP consortia are addressing many of these issues.