IC process modeling and topography design

The device features in the third dimension in VLSI affect packing density and circuit performance. Establishing techniques to characterize and design these nonplanar device features is a major goal of the research on IC process modeling and simulation. Simulation is well accepted as a means of optimizing individual lithography, etching, and deposition processes. It is also well suited for studying the complex tradeoffs between conflicting physical mechanisms in the context of complete multistep process sequences. The success of modeling and simulation has created a demand for more extensive models and new applications. IC process modeling and simulation will not only contribute heavily to technology design but also offers a potential window through the layout role bottleneck for more complete design insight and optimization.

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