Practical experiences with standard-cell based datapath design tools: do we really need regular layouts?

Commercial tools for standard-cell based datapath design are here classed according to design flows, and the advantages of each class are discussed with the results of two test circuits. Algorithmic generation of netlists and of relative cell placement can help reducing area but, contrary to common belief, appears often detrimental to speed. Extraction of regularity from synthesized netlists is difficult and requires counterproductive simplifications to the synthesis process. Most promising are synthesis tools which can generate placement data; yet, no tool of this class appears ready today.

[1]  Jalil Fadavi-Ardekani,et al.  M*N Booth encoded multiplier generator using optimized Wallace trees , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[2]  Lawrence L. Larmore,et al.  Layout placement for sliced architecture , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Tobias G. Noll,et al.  A datapath generator for full-custom macros of iterative logic arrays , 1997, Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors.

[4]  Stamatis Vassiliadis,et al.  Hard-Wired Multipliers with Encoded Partial Products , 1991, IEEE Trans. Computers.

[5]  Neil Weste,et al.  Principles of CMOS VLSI Design , 1985 .

[6]  C. Y. Roger Chen,et al.  LILA: layout generation for iterative logic arrays , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Jalil Fadavi-Ardekani.  M×N Booth encoded multiplier generator using optimized Wallace trees , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Vojin G. Oklobdzija,et al.  A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach , 1996, IEEE Trans. Computers.