Clock-less Design for Reconfigurable Floating Point Multiplier

Floating point multiplication has became a common element in signal processing, image processing, filters and real time data processing digital circuits. This element highly influence the performance of the whole design in the form of area and power used. This paper presents a asynchronous reconfigurable approach to design a floating point multiplier for IEEE 754 double precision or two single precision numbers in parallel. The proposed design is a better solution in terms of area and power efficiency. The design is synthesized on XST of Xilinx ISE tool for vertex 2pro FPGA board and simulated on ModelSim. The proposed multiplier comprises of two units (i) Multiply-Add unit and (ii) Aligner-normalizing unit. This design can work up to 229.106 MHz and uses 1369 Slices of Virtex 2 Pro FPGA. Keywords-component, Asynchronous, Reconfigurable, Floating point, FPGA, pipelining and parallel Architecture.