Physical Modeling of Bitcell Stability in Subthreshold SRAMs for Leakage–Area Optimization under PVT Variations

Subthreshold SRAM design is crucial for addressing the memory bottleneck in energy constrained applications. While statistical optimization can be applied based on Monte-Carlo (MC) simulation, exploration of bitcell design space is time consuming. This paper presents a framework for model-based design and optimization of subthreshold SRAM bitcells under random PVT variations. By incorporating key design and process features, a physical model of bitcell static noise margin (SNM) has been derived analytically. It captures intra-die SNM variations by the combination of a folded-normal distribution and a non-central chi-squared distribution. Validations with MC simulation show its accuracy of modeling SNM distributions down to 25mV beyond 6-sigma for typical bitcells in 28nm. Model-based tuning of subthreshold SRAM bitcells is investigated for design tradeoff between leakage, area and stability. When targeting a specific SNM constraint, we show that an optimal standby voltage exists which offers minimum bitcell leakage power – any deviation above or below increases the power consumption. When targeting a specific standby voltage, our design flow identifies bitcell instances of 12× less leakage power or 3× reductions in area as compared to the minimum-length design.

[1]  Kaushik Roy,et al.  Significance driven hybrid 8T-6T SRAM for energy-efficient synaptic storage in artificial neural networks , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[2]  Chien-Yu Lu,et al.  A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Armin Tajalli,et al.  Extreme Low-Power Mixed Signal IC Design: Subthreshold Source-Coupled Circuits , 2010 .

[4]  A.P. Chandrakasan,et al.  A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation , 2007, IEEE Journal of Solid-State Circuits.

[5]  Toshiro Hiramoto,et al.  Re-Examination of Impact of Intrinsic Dopant Fluctuations on Static RAM (SRAM) Static Noise Margin , 2005 .

[6]  Ming-Hsien Tu,et al.  40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  Rob A. Rutenbar,et al.  Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Jan M. Rabaey,et al.  Standby supply voltage minimization for deep sub-micron SRAM , 2005, Microelectron. J..

[9]  Chien-Yu Lu,et al.  A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing , 2012, IEEE Journal of Solid-State Circuits.

[10]  Mohab Anis,et al.  Statistical Design of the 6T SRAM Bit Cell , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[11]  Mohammad Sharifkhani,et al.  Statistical Analysis of Read Static Noise Margin for Near/Sub-Threshold SRAM Cell , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Julien Zory,et al.  Static Noise Margin Analysis of Sub-threshold SRAM Cells in Deep Sub-micron Technology , 2005, PATMOS.

[13]  S. Roy,et al.  The impact of random doping effects on CMOS SRAM cell , 2004, Proceedings of the 30th European Solid-State Circuits Conference.

[14]  Lara Dolecek,et al.  Breaking the simulation barrier: SRAM evaluation through norm minimization , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[15]  Meng-Fan Chang,et al.  A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications , 2011, IEEE Journal of Solid-State Circuits.

[16]  Anna W. Topol,et al.  Stable SRAM cell design for the 32 nm node and beyond , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[17]  A.P. Chandrakasan,et al.  Static noise margin variation for sub-threshold SRAM in 65-nm CMOS , 2006, IEEE Journal of Solid-State Circuits.

[18]  A.P. Chandrakasan,et al.  A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy , 2008, IEEE Journal of Solid-State Circuits.

[19]  Boris Murmann,et al.  SRAM voltage scaling for energy-efficient convolutional neural networks , 2017, 2017 18th International Symposium on Quality Electronic Design (ISQED).

[20]  Bo Zhai,et al.  A Variation-Tolerant Sub-200 mV 6-T Subthreshold SRAM , 2008, IEEE Journal of Solid-State Circuits.

[21]  Pinaki Mazumder,et al.  Modeling and Mitigation of Static Noise Margin Variation in Subthreshold SRAM Cells , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

[22]  Sani R. Nassif,et al.  Statistical analysis of SRAM cell stability , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[23]  Francky Catthoor,et al.  Ultra Low-Energy SRAM Design for Smart Ubiquitous Sensors , 2012, IEEE Micro.

[24]  Andrew R. Brown,et al.  Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs , 2003 .

[25]  Antonio Petraglia,et al.  Analytic boundaries for 6T-SRAM design in standby mode , 2016, 2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI).

[26]  Hidetoshi Onodera,et al.  A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region , 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

[27]  Rajiv V. Joshi,et al.  Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[28]  Kaushik Roy,et al.  A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[29]  J. Meindl,et al.  The impact of intrinsic device fluctuations on CMOS SRAM cell stability , 2001, IEEE J. Solid State Circuits.

[30]  Kaushik Roy,et al.  Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[31]  Anantha Chandrakasan,et al.  Challenges and Directions for Low-Voltage SRAM , 2011, IEEE Design & Test of Computers.

[32]  Rob A. Rutenbar,et al.  Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[33]  E. Seevinck,et al.  Static-noise margin analysis of MOS SRAM cells , 1987 .

[34]  Jan M. Rabaey,et al.  Low Power Design Essentials , 2009, Series on Integrated Circuits and Systems.

[35]  Toshiro Hiramoto,et al.  Re-examination of Impact of Intrinsic Dopant Fluctuations on SRAM Static Noise Margin , 2004 .