On the Reliability of Majority Gates Full Adders
暂无分享,去创建一个
[1] V. Beiu,et al. On Practical Multiplexing Issues , 2006, 2006 Sixth IEEE Conference on Nanotechnology.
[2] Massimo Alioto,et al. Analysis and comparison on full adder block in submicron technology , 2002, IEEE Trans. Very Large Scale Integr. Syst..
[3] Lynn Conway,et al. Introduction to VLSI systems , 1978 .
[4] V. Beiu,et al. Reliability the Fourth Optimization Pillar of Nanoelectronics , 2007, 2007 IEEE International Conference on Signal Processing and Communications.
[5] V. Beiu,et al. Accurate Nano-Circuits Reliability Evaluations Based on Combining Numerical Simulations with Monte Carlo , 2007, 2007 2nd International Design and Test Workshop.
[6] Mo Liu,et al. Reliability and Defect Tolerance in Metallic Quantum-dot Cellular Automata , 2007, J. Electron. Test..
[7] Omid Kavehei,et al. A Novel CMOS Full Adder , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).
[8] V. Beiu,et al. On the Reliability of Four Full Adder Cells , 2007, 2007 Innovations in Information Technologies (IIT).
[9] John P. Hayes,et al. Logic circuit testing for transient faults , 2005, European Test Symposium (ETS'05).
[10] J.M. Quintana,et al. Low-power logic styles for full-adder circuits , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).
[11] Snorre Aunet,et al. Six subthreshold full adder cells characterized in 90 nm CMOS technology , 2006, 2006 IEEE Design and Diagnostics of Electronic Circuits and systems.
[12] Magdy Bayoumi,et al. A novel high-performance CMOS 1-bit full-adder cell , 2000 .
[13] G.E. Moore,et al. Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.
[14] Valeriu Beiu,et al. What von Neumann Did Not Say About Multiplexing Beyond Gate Failures - The Gory Details , 2007, IWANN.
[15] Ali Afzali-Kusha,et al. Subthreshold 1-Bit Full Adder Cells in sub-100 nm Technologies , 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).
[16] J. E. Mooij,et al. Single-electron inverter , 2000, cond-mat/0011520.
[17] V. Beiu,et al. A fresh look at majority multiplexing when devices get into the picture , 2007, 2007 7th IEEE Conference on Nanotechnology (IEEE NANO).
[18] Yin-Tsung Hwang,et al. A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.
[19] Konstantin K. Likharev,et al. Single-electron devices and their applications , 1999, Proc. IEEE.
[20] Andrew R. Brown,et al. Intrinsic fluctuations in sub 10-nm double-gate MOSFETs introduced by discreteness of charge and matter , 2002 .
[21] Lorenzo Alvisi,et al. Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.
[22] Magdy A. Bayoumi,et al. A new full adder cell for low-power applications , 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).
[23] Snorre Aunet,et al. Small Fan-in Floating-Gate Circuits with Application to an Improved Adder Structure , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).
[24] Valeriu Beiu,et al. Serial Addition: Locally Connected Architectures , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.
[25] Massimo Alioto,et al. Very fast carry energy efficient computation based on mixed dynamic=transmission-gate full adders , 2007 .
[26] John R. Tucker,et al. Complementary digital logic based on the ``Coulomb blockade'' , 1992 .
[27] Siegfried Selberherr,et al. SIMON-A simulator for single-electron tunnel devices and circuits , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[28] Yoshihito Amemiya,et al. Single-Electron Majority Logic Circuits , 1997 .
[29] Massimo Macucci,et al. Critical assessment of the QCA architecture as a viable alternative to large scale integration , 2004 .
[30] Chunhong Chen,et al. Performance Evaluation and Optimization of Full Adders with Single-Electron Technology , 2006, 2006 Canadian Conference on Electrical and Computer Engineering.
[31] L. Kish. End of Moore's law: thermal (noise) death of integration in micro and nano electronics , 2002 .
[32] T.S. Lande,et al. Multifunction subthreshold gate used for a low power full adder , 2004, Proceedings Norchip Conference, 2004..
[33] Israel Koren. Computer arithmetic algorithms , 1993 .
[34] . T.Vigneswaran,et al. A Novel Low Power, High Speed 14 Transistor CMOS Full Adder Cell with 50% Improvement in Threshold Loss Problem , 2008 .
[35] P. D. Tougaw,et al. Logical devices implemented using quantum cellular automata , 1994 .
[36] Gregory S. Snider,et al. A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology , 1998 .
[37] Cristian Constantinescu,et al. Trends and Challenges in VLSI Circuit Reliability , 2003, IEEE Micro.
[38] V. Beiu,et al. Design and analysis of SET circuits: using MATLAB modules and SIMON , 2004, 4th IEEE Conference on Nanotechnology, 2004..
[39] J. Hayes,et al. Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models , 2003 .
[40] J. Neumann. Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components , 1956 .
[41] M. A. Bayoumi,et al. A framework for fair performance evaluation of 1-bit full adder cells , 1999, 42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356).
[42] A. S. Sadek,et al. Parallel information and computation with restitution for noise-tolerant nanoscale logic networks , 2003 .
[43] Magdy A. Bayoumi,et al. Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[44] Yasuo Takahashi,et al. Multigate single-electron transistors and their application to an exclusive-OR gate , 2000 .
[45] Kamal Kumar Sharma. Simple and systematic design of FA cell using K map , 2005, IEICE Electron. Express.
[46] Yngvar Berg,et al. A novel floating-gate multiple-valued CMOS full-adder , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).
[47] Massimo Alioto,et al. High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology , 2007, 2007 IEEE International Symposium on Circuits and Systems.
[48] J. Meindl,et al. Limits on silicon nanoelectronics for terascale integration. , 2001, Science.
[49] . T.Vigneswaran,et al. A Novel Low Power and High Performance 14 Transistor CMOS Full Adder Cell , 2006 .
[50] Tetsuya Asai,et al. A majority-logic device using an irreversible single-electron box , 2003 .
[51] Tarek Darwish,et al. Performance analysis of low-power 1-bit CMOS full adder cells , 2002, IEEE Trans. Very Large Scale Integr. Syst..
[52] Milos D. Ercegovac,et al. Digital Arithmetic , 2003, Wiley Encyclopedia of Computer Science and Engineering.
[53] Valeriu Beiu,et al. Gate Failures Effectively Shape Multiplexing , 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
[54] Wei Wang,et al. Quantum-dot cellular automata adders , 2003, 2003 Third IEEE Conference on Nanotechnology, 2003. IEEE-NANO 2003..
[55] John P. Hayes,et al. Accurate reliability evaluation and enhancement via probabilistic transfer matrices , 2005, Design, Automation and Test in Europe.
[56] S. Roy,et al. Majority multiplexing-economical redundant fault-tolerant designs for nanoarchitectures , 2005, IEEE Transactions on Nanotechnology.
[57] Hiroshi Inokawa,et al. Binary adders of multigate single-electron transistors: specific design using pass-transistor logic , 2002 .
[58] V. Beiu,et al. On single-electron technology full adders , 2004, IEEE Transactions on Nanotechnology.