SoC design methodologies

As the complexity of integrated circuit increases, it is becoming more and more difficult to design a complete system Erom scratch. To make the design manageable, a good methodology is needed. This session starts with a paper introducing a system level design language. SoC design may contain analog IP cores. The second paper proposes a new methodology for digital and analog codesign. Then the experience with a design methodology used to a industrial ATM design is discussed. Finally a VHDL package that allows event-driven simulator to accurately simulate transistor level description is presented.