Multi-input strobed analogue comparator

The architecture presented combines a cross-coupled 'winner takes all' circuit with a multi-input digital latch. Only one of the digital outputs is a logic 'one', corresponding to the largest analogue input. A five-input prototype was built using a 2 /spl mu/m CMOS process. The 300/spl times/280 /spl mu/m/sup 2/ circuit dissipates 1 mW from a single 5 V supply at a maximum clock frequency of 10 MHz.