Modular paging with dynamic TLB partitioning for embedded real-time systems

Modern embedded systems are composed of hard real-time tasks, soft real-time tasks and even non real-time tasks. A key requirement for system reliability is inter-task memory protection to prevent the spreading of faults across address spaces. Due to the lack of suitable approaches to enable virtual memory under hard real-time constraints and to support high flexibility for soft and non real-time tasks, we propose a modular page table approach with dynamic TLB partitioning. Different tasks are handled variably, depending on their real time constraints.

[1]  Trevor N. Mudge,et al.  A look at several memory management units, TLB-refill mechanisms, and page table organizations , 1998, ASPLOS VIII.

[2]  Mark D. Hill,et al.  Surpassing the TLB performance of superpages with less operating system support , 1994, ASPLOS VI.

[3]  Xiangrong Zhou,et al.  Energy-efficient address translation for virtual memory support in low-power and real-time embedded processors , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[4]  Klaus H. Ecker,et al.  Robust partitioning for reliable real-time systems , 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

[5]  Neil C. Audsley,et al.  Predictable and efficient virtual addressing for safety-critical real-time systems , 2001, Proceedings 13th Euromicro Conference on Real-Time Systems.

[6]  Kang G. Shin,et al.  On memory protection in real-time OS for small embedded systems , 1997, Proceedings Fourth International Workshop on Real-Time Computing Systems and Applications.

[7]  David Channon,et al.  Performance analysis of re-configurable partitioned TLBs , 1997, Proceedings of the Thirtieth Hawaii International Conference on System Sciences.

[8]  Mark D. Hill,et al.  Tradeoffs in supporting two page sizes , 1992, ISCA '92.

[9]  Trevor N. Mudge,et al.  Virtual memory in contemporary microprocessors , 1998, IEEE Micro.

[10]  Ryan N. Rakvic,et al.  A comprehensive study of hardware/software approaches to improve TLB performance for java applications on embedded systems , 2006, MSPC '06.