Josephson-CMOS Hybrid Memory With Nanocryotrons

We present hybridization of Josephson, CMOS, and nanocryotron (nTron) devices for a large-scale cryogenic memory application. The memory system proposed here is dynamic random access memory composed of address decoders based on an energy-efficient rapid single-flux-quantum logic, nTron line drivers, a CMOS memory cell array, and Josephson current sensors. Because drivers with voltage amplification and decoders are the major causes of power dissipation in the conventional Josephson-CMOS hybrid memory, drastic reduction in power consumption is expected. We show estimates that the power consumption of a 16-Mb memory is reduced to 1.36–2.77 mW, approximately 1/12 of the conventional Josephson-CMOS hybrid memory, and the access time is 0.78 ns for a read operation, when we assume a 65-nm CMOS process and a 1.0-<inline-formula><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula>m Nb/AlO<inline-formula> <tex-math notation="LaTeX">$_x$</tex-math></inline-formula>/Nb process. In the preliminary experiment, we fabricated nTrons using NbTiN thin film that are suitable for hybrid memory implementation, and measured with eight-transistor static random access memory cells fabricated using the Rohm 0.18-<inline-formula><tex-math notation="LaTeX">$\mu$ </tex-math></inline-formula>m CMOS process. We successfully triggered the nTron into the normal state, and observed output voltage of <inline-formula><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula>0.1 V at 13.5 K. The experimental results support the potential of the hybrid memory using NbTiN nTrons.