Optimizing ODT condition and Driver's turn-on resistance to achieve SI of LPDDR dual rank configuration

Increasing the clock frequency of IO system with LPDDR4 and LPDDR5 in SOC (system on a chip) has escalated the importance of SI on the functional stability and low power operation of the circuit blocks, because the challenge to design and verification of SDN (signal delivery network) of SOC, DRAM and system-level PCB is rising higher and higher with limited cost budget and design cycle-time. Therefore, SDN design should include the proper channel design satisfying signal loss and adequate cross-talk, as well as proper ODT scheme with optimum turn-on resistance of driver. In this work, a design methodology to achieve signal integrity up-to 6.4Gbps/pin dual rank system with LPDDR DRAM and DRAM controller has been presented based on frequency-domain approach with voltage transfer function. It has been demonstrated that optimizing ODT condition of target and nontarget terminal and turn on resistance of Tx (transmitter) is achieved before time-domain simulation which generally requires huge computation time.

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