Real-world charged board model (CBM) failures

ICs that are robust to ESD at the component-level may be damaged by ESD at the board-level. Two case studies show that real-world Charged Board Model (CBM) ESD damage is typically more severe than HBM or CDM damage. Consequently, CBM damage can be easily mistaken for EOS damage. A high-capacitance yet compact PCB evaluation board facilitates qualitative CBM testing using conventional CDM test systems. Based on the case studies and CBM test results, guidelines are provided on how to minimize the likelihood of real-world CBM failures.

[1]  Roger J. Peirce,et al.  The most common causes of ESD damage: after studying hundreds of facilities, a veteran ESD consultant and auditor shares his top 23 causes of damage to ESD-sensitive parts. (Coping with ESD) , 2002 .

[2]  D. L. Jin.  FCBM-a field-induced charged-board model for electrostatic discharges , 1992 .

[3]  A. Olney.  A combined socketed and non-socketed CDM test approach for eliminating real-world CDM failures , 1996, 1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[4]  Kaustav Banerjee,et al.  Microanalysis of VLSI interconnect failure modes under short-pulse stress conditions , 2000, 2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059).

[5]  Jon Barth,et al.  Correlation considerations II: Real HBM to HBM testers , 2002, 2002 Electrical Overstress/Electrostatic Discharge Symposium.

[6]  D.C. Smith,et al.  ESD immunity in system designs, system field experiences and effects of PWB layout , 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

[7]  D. L. Lin,et al.  Off-chip protection: Shunting of ESD current by metal fingers on integrated circuits and printed circuit boards , 1995 .

[8]  G. Weil.  Characterization and test methods for printed circuit board ESD , 1990, IEEE International Symposium on Electromagnetic Compatibility.

[9]  Alan Righter,et al.  A new ESD model: The Charged Strip Model , 2002, 2002 Electrical Overstress/Electrostatic Discharge Symposium.

[10]  Sung-Mo Kang,et al.  Chip-level charged-device modeling and simulation in CMOS integrated circuits , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..