Fast prototyping of asynchronous logic

Digital designers increasingly use asynchronous circuit techniques to combat the design complexities, energy consumption, and manufacturing variabilities that affect modern VLSI circuits. Existing commercial FPGAs, due to their clocked architectures, cannot efficiently prototype asynchronous logic. This dissertation investigates asynchronous FPGA architectures and automated methods for their configuration, with the goal of quickly prototyping asynchronous designs. First, we present a new asynchronous FPGA architecture that has integrated pipelining support and is configurable at the pipeline-stage level. This pipelined asynchronous FPGA has the property of slack elasticity and hence does not need explicit retiming registers to prototype high-speed pipelined designs. We report performance numbers that, for the first time, are competitive with and actually better than clocked FPGA architectures, and that are also competitive with full custom asynchronous design. Second, we discuss logic synthesis methods for automatically mapping asynchronous designs to these FPGA architectures. We present a high-level synthesis technique that creates dataflow graphs of asynchronous computations and projects them onto a regular set of concurrent asynchronous pipeline stages. These pipelines can then be mapped to our asynchronous FPGAs using standard clocked place-and-route tools.