Design of Address Generators Using Multiple LUT Cascade on FPGA

This paper presents multiple LUT cascade to realize an address generator that produces unique addresses ranging from 1 to k for k distinct input vectors. We implemented six kinds of address generators using multiple LUT cascades, Xilinx’s CAM (Xilinx IP core), and an address generator using registers and gates on Xilinx Spartan-3 FPGAs. One of our implementations has 76% more throughput, 29.5 times more throughput/slice, and 1.35 times more throughput/memory than Xilinx’s CAM.