Upgradation of Design for Testability (DFT) Analysis Flow

[1]  Irith Pomeranz,et al.  Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Irith Pomeranz,et al.  Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Rubin A. Parekhji,et al.  Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems , 2000, Proceedings of the Ninth Asian Test Symposium.

[4]  Sarma B. K. Vrudhula,et al.  Fault Coverage and Test Length Estimation for Random Pattern Testing , 1995, IEEE Trans. Computers.

[5]  Javier Uceda,et al.  A fault model for VHDL descriptions at the register transfer level , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.

[6]  S. Hassan,et al.  Automatic test pattern generation from high level specifications , 2003, 2003 46th Midwest Symposium on Circuits and Systems.

[7]  Weiwei Mao,et al.  Improving gate level fault coverage by RTL fault grading , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[8]  Krishna R. Pattipati,et al.  Test sequencing problems arising in test planning and design for testability , 1999, IEEE Trans. Syst. Man Cybern. Part A.

[9]  Janak H. Patel,et al.  Addressing design for testability at the architectural level , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Irith Pomeranz,et al.  Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Vishwani D. Agrawal,et al.  Tutorial: Delay Fault Models and Coverage , 1998 .

[12]  Vishwani D. Xgratval Tutorial: Delay Fault Models and Coverage , 1997 .

[13]  Malgorzata Marek-Sadowska,et al.  Improving the Resolution of Single-Delay-Fault Diagnosis , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Sanghyeon Baeg,et al.  A cost-effective design for testability: clock line control and test generation using selective clocking , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Xiaoqing Wen,et al.  Design for Testability , 2006 .

[16]  Tom Chen,et al.  Fault coverage estimation for early stage of VLSI design , 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

[17]  Spyros Tragoudas,et al.  Function-based compact test pattern generation for path delay faults , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  Sujit Dey,et al.  A low overhead design for testability and test generation technique for core-based systems , 1997, Proceedings International Test Conference 1997.

[19]  Thomas W. Williams Design for Testability , 1982, 19th Design Automation Conference.

[20]  Miron Abramovici Dos and Don'ts in computing fault coverage , 1993, Proceedings of IEEE International Test Conference - (ITC).

[21]  Sujit Dey,et al.  A low overhead design for testability and test generation technique for core-based systems-on-a-chip , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[22]  Abhijit Chatterjee,et al.  Design for testability and built-in self-test of mixed-signal circuits: a tutorial , 1997, Proceedings Tenth International Conference on VLSI Design.

[23]  Ian G. Harris,et al.  A method for the evaluation of behavioral fault models , 2003, Eighth IEEE International High-Level Design Validation and Test Workshop.