An embedded energy monitoring circuit for a 128kbit SRAM with body-biased sense-amplifiers
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[1] Anantha P. Chandrakasan,et al. A 45nm 0.5V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier , 2009, 2009 IEEE Asian Solid-State Circuits Conference.
[2] W. Dehaene,et al. A 3.6pJ/access 480MHz, 128Kbit on-Chip SRAM with 850MHz boost mode in 90nm CMOS with tunable sense amplifiers to cope with variability , 2008, ESSCIRC 2008 - 34th European Solid-State Circuits Conference.
[3] Nathan Ickes,et al. A 10 pJ/cycle ultra-low-voltage 32-bit microprocessor system-on-chip , 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).
[4] William J. Bowhill,et al. A 32nm 3.1 billion transistor 12-wide-issue Itanium® processor for mission-critical servers , 2011, 2011 IEEE International Solid-State Circuits Conference.
[5] George Kurian,et al. Self-aware computing in the Angstrom processor , 2012, DAC Design Automation Conference 2012.
[6] A.P. Chandrakasan,et al. Minimum Energy Tracking Loop With Embedded DC–DC Converter Enabling Ultra-Low-Voltage Operation Down to 250 mV in 65 nm CMOS , 2008, IEEE Journal of Solid-State Circuits.
[7] A.P. Chandrakasan,et al. A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy , 2008, IEEE Journal of Solid-State Circuits.
[8] Joseph A. Paradiso,et al. Energy Metering for Free: Augmenting Switching Regulators for Real-Time Monitoring , 2008, 2008 International Conference on Information Processing in Sensor Networks (ipsn 2008).