Design and Implementation of Scalable Online Evolvable Hardware Pattern Recognition Systems

Evolvable hardware (EHW) is a method where hardware is designed and/or modified automatically by optimization algorithms called evolutionary algorithms (EAs). The results so far are promising but somewhat limited partly because of a scalability problem of the EHW design method. It is hard to generate circuits which are capable of handling large real-world problems in a competitive manner. Schemes for dealing with the scalability problem have been proposed earlier, however the application of these to run-time adaptive EHW systems has been limited. This thesis addresses the challenge to generate autonomous run-time adaptive digital EHW systems for solving large real-world problems. The challenge consists of dealing with the lack of scalability in EAs, combined with the challenge of designing an adaptive hardware architecture for the evolution. Specifically, hardware classifiers are developed for accurate classification of inputs with a large number of features. For experimentation with online adaptation, an on-chip evolutionary system has been proposed and implemented, making use of an on-chip processor. In order to overcome the scalability problem, the use of data buses and high-level building blocks has been investigated. Further, these elements have been combined with incremental evolution into a specialized high-speed classifier architecture for online evolution. The architecture has been applied to several difficult application benchmarks and compared to traditional approaches as well as previously presented EHW approaches. The work has resulted in a flexible system for on-chip evolution. The proposed online architecture is capable of classifying problems with a larger number of inputs than previous online EHW classifiers, and it gives a higher accuracy for these problems than previously presented EHW systems. These systems have often been based on offline evolution – regarded as less challenging than online evolution. In addition, the amount of evaluations needed for the evolutionary search is low compared to previously presented systems. The system has also shown to be competitive to traditional classification approaches for the applied benchmarks.

[1]  Isamu Kajitani,et al.  Hardware Evolution at Function Level , 1996, PPSN.

[2]  I. Yoshihara,et al.  Evolvable sonar spectrum discrimination chip designed by genetic algorithm , 1999, IEEE SMC'99 Conference Proceedings. 1999 IEEE International Conference on Systems, Man, and Cybernetics (Cat. No.99CH37028).

[3]  Tughrul Arslan,et al.  Evolvable Components—From Theory to Hardware Implementations , 2005, Genetic Programming and Evolvable Machines.

[4]  Mehrdad Salami,et al.  Data Compression for Digital Color Electrophotographic Printer with Evolvable Hardware , 1998, ICES.

[5]  Julian Francis Miller,et al.  Evolution and Acquisition of Modules in Cartesian Genetic Programming , 2004, EuroGP.

[6]  Lukás Sekanina,et al.  Evolutionary Design of Arbitrarily Large Sorting Networks Using Development , 2005, Genetic Programming and Evolvable Machines.

[7]  Julian Francis Miller,et al.  Towards the automatic design of more efficient digital circuits , 2000, Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware.

[8]  Adam Megacz,et al.  A Library and Platform for FPGA Bitstream Manipulation , 2007, 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007).

[9]  Jim Torresen,et al.  Two-Step Incremental Evolution of a Prosthetic Hand Controller Based on Digital Logic Gates , 2001, ICES.

[10]  Dario Floreano,et al.  POEtic Tissue: An Integrated Architecture for Bio-inspired Hardware , 2003, ICES.

[11]  Raoul Tawel,et al.  Evolutionary experiments with a fine-grained reconfigurable architecture for analog and digital CMOS circuits , 1999, Proceedings of the First NASA/DoD Workshop on Evolvable Hardware.

[12]  Gunnar Tufte,et al.  Towards Development on a Silicon-based Cellular Computing Machine , 2005, Natural Computing.

[13]  Jim Torresen,et al.  Evolving Multiplier Circuits by Training Set and Training Vector Partitioning , 2003, ICES.

[14]  Xin Yao,et al.  The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing , 1999, IEEE Trans. Computers.

[15]  Upegui Posada,et al.  Dynamically reconfigurable bio-inspired hardware , 2006 .

[16]  Gunnar Tufte,et al.  Biologically-Inspired: A Rule-Based Self-Reconfiguration of a Virtex Chip , 2004, International Conference on Computational Science.

[17]  Taro Nakamura,et al.  Genetic Algorithm-Based Methodology for Pattern Recognition Hardware , 2000, ICES.

[18]  Lukas Sekanina,et al.  DESIGN OF THE SPECIAL FAST RECONFIGURABLE CHIP USING COMMON FPGA , 2001 .

[19]  Gunnar Tufte,et al.  Building Knowledge into Developmental Rules for Circuit Design , 2003, ICES.

[20]  Jim Tørresen,et al.  A Divide-and-Conquer Approach to Evolvable Hardware , 1998, ICES.

[21]  Adrian Thompson,et al.  Silicon evolution , 1996 .

[22]  Adrian Stoica,et al.  Evolvable hardware solutions for extreme temperature electronics , 2001, Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001.