A reduced voltage swing circuit using a single supply to enable lower voltage operation for SRAM-based memory
暂无分享,去创建一个
[1] K. Roy,et al. Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS , 2007, IEEE Journal of Solid-State Circuits.
[2] K. Takeda,et al. A read-static-noise-margin-free SRAM cell for low-V/sub dd/ and high-speed applications , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
[3] J.G. Massey,et al. NBTI: what we know and what we need to know - a tutorial addressing the current understanding and challenges for the future , 2004, IEEE International Integrated Reliability Workshop Final Report, 2004.
[4] K. Nii,et al. 90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique , 2006, IEEE Journal of Solid-State Circuits.
[5] Nomura Masahiro,et al. A Read-Static-Noise-Margin-Free SRAM cell for low-Vdd and High-speed applications , 2005 .
[6] Asim J. Al-Khalili,et al. Performance analysis and design of optimized static random access memory (SRAM) , 1993 .
[7] Kaushik Roy,et al. Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[8] Volkan Kursun,et al. Dynamic wordline voltage swing for low leakage and stable static memory banks , 2008, 2008 IEEE International Symposium on Circuits and Systems.
[9] William J. Bowhill,et al. Design of High-Performance Microprocessor Circuits , 2001 .
[10] K. Ishibashi,et al. A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits , 2007, IEEE Journal of Solid-State Circuits.
[11] V. Kursun,et al. Stability enhancement techniques for nanoscale SRAM circuits: A comparison , 2008, 2008 International SoC Design Conference.
[12] T. Karnik,et al. Read and write circuit assist techniques for improving Vccmin of dense 6T SRAM cell , 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.
[13] James Tschanz,et al. Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[14] E. Seevinck,et al. Static-noise margin analysis of MOS SRAM cells , 1987 .
[15] N. Vallepalli,et al. A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply , 2005, IEEE Journal of Solid-State Circuits.
[16] David Harris,et al. CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .
[17] Jim Handy,et al. The cache memory book , 1993 .
[18] Koji Nii,et al. A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[19] Seung-Ho Song,et al. Implementation of low-voltage static RAM with enhanced data stability and circuit speed , 2009, Microelectron. J..
[20] Tsong Yueh Chen,et al. On-chip triple-error correction and quadruple-error detection ECC structure for ultra-large, single-chip memories , 2000 .
[21] T. Nigam,et al. SRAM Variability and Supply Voltage Scaling Challenges , 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.
[22] Volkan Kursun,et al. Stability Enhancement Techniques for Nanoscale SRAM Circuits , 2008 .
[23] Sachin S. Sapatnekar,et al. Impact of NBTI on SRAM read stability and design for reliability , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).
[24] Baker Mohammad,et al. Cache Design for Low Power and High Yield , 2008, ISQED 2008.