An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data Compression for Neural Recording

Low power consumption per channel and data rate minimization are two key challenges which need to be addressed in future generations of neural recording systems (NRS). Power consumption can be reduced by avoiding unnecessary processing whereas data rate is greatly decreased by sending spike time-stamps along with spike features as opposed to raw digitized data. Dynamic range in NRS can vary with time due to change in electrode-neuron distance or background noise, which demands adaptability. An analog-to-digital converter (ADC) is one of the most important blocks in a NRS. This paper presents an 8-bit SAR ADC in 0.13- μm CMOS technology along with input and reference buffer. A novel energy efficient digital-to-analog converter switching scheme is proposed, which consumes 37% less energy than the present state-of-the-art. The use of a ping-pong input sampling scheme is emphasized for multichannel input to alleviate the bandwidth requirement of the input buffer. To reduce the data rate, the A/D process is only enabled through the in-built background noise rejection logic to ensure that the noise is not processed. The ADC resolution can be adjusted from 8 to 1 bit in 1-bit step based on the input dynamic range. The ADC consumes 8.8 μW from 1 V supply at 1 MS/s speed. It achieves effective number of bits of 7.7 bits and FoM of 42.3 fJ/conversion-step.

[1]  Ying Yao,et al.  An Implantable 64-Channel Wireless Microsystem for Single-Unit Neural Recording , 2009, IEEE Journal of Solid-State Circuits.

[2]  Anantha Chandrakasan,et al.  A resolution-reconfigurable 5-to-10b 0.4-to-1V power scalable SAR ADC , 2011, 2011 IEEE International Solid-State Circuits Conference.

[3]  W. Liu,et al.  A 128-Channel 6 mW Wireless Neural Recording IC With Spike Feature Extraction and UWB Transmitter , 2009, IEEE Transactions on Neural Systems and Rehabilitation Engineering.

[4]  B.P. Ginsburg,et al.  500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC , 2007, IEEE Journal of Solid-State Circuits.

[5]  V. Chaturvedi,et al.  Energy efficient asymmetric binary search switching technique for SAR ADC , 2010 .

[6]  A.P. Chandrakasan,et al.  An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes , 2007, IEEE Journal of Solid-State Circuits.

[7]  J. Vibert,et al.  Spike separation in multiunit records: a multivariate analysis of spike descriptive parameters. , 1979, Electroencephalography and clinical neurophysiology.

[8]  S. Mitra,et al.  Analysis of mismatch effects among A/D converters in a time-interleaved waveform digitizer , 1991 .

[9]  Mohamad Sawan,et al.  Setting Adaptive Spike Detection Threshold for Smoothed TEO Based on Robust Statistics Theory , 2012, IEEE Transactions on Biomedical Engineering.

[10]  R. R. Harrison,et al.  A low-power low-noise CMOS amplifier for neural recording applications , 2003, IEEE J. Solid State Circuits.

[11]  Eric A. M. Klumperink,et al.  A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[12]  R. Olsson,et al.  A three-dimensional neural recording microsystem with implantable data compression circuitry , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[13]  G. Promitzer.  12 bit low power fully differential switched capacitor non-calibrating successive approximation ADC with 1MS/s , 2000, Proceedings of the 26th European Solid-State Circuits Conference.

[14]  R.R. Harrison,et al.  Wireless Neural Recording With Single Low-Power Integrated Circuit , 2009, IEEE Transactions on Neural Systems and Rehabilitation Engineering.

[15]  Chorng-Kuang Wang,et al.  A 8-bit 500-KS/s low power SAR ADC for bio-medical applications , 2007, 2007 IEEE Asian Solid-State Circuits Conference.

[16]  Maysam Ghovanloo,et al.  A flexible clockless 32-ch simultaneous wireless neural recording system with adjustable resolution , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[17]  Kristofer S. J. Pister,et al.  An ultralow-energy ADC for Smart Dust , 2003, IEEE J. Solid State Circuits.

[18]  Soon-Jyh Chang,et al.  A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure , 2010, IEEE Journal of Solid-State Circuits.

[19]  Patrick D. Wolf,et al.  Evaluation of spike-detection algorithms fora brain-machine interface application , 2004, IEEE Transactions on Biomedical Engineering.

[20]  Jan Craninckx,et al.  A 70dB DR 10b 0-to-80MS/s current-integrating SAR ADC with adaptive dynamic range , 2012, 2012 IEEE International Solid-State Circuits Conference.

[21]  Pedram Mohseni,et al.  A Battery-Powered Activity-Dependent Intracortical Microstimulation IC for Brain-Machine-Brain Interface , 2011, IEEE Journal of Solid-State Circuits.

[22]  Degang Chen,et al.  A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs , 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

[23]  D.A. Hodges,et al.  All-MOS charge-redistribution analog-to-digital conversion techniques. II , 1975, IEEE Journal of Solid-State Circuits.

[24]  Kari Halonen,et al.  A mismatch insensitive CMOS dynamic comparator for pipeline A/D converters , 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).

[25]  Bharadwaj S. Amrutur,et al.  An Area-Efficient Noise-Adaptive Neural Amplifier in 130 nm CMOS Technology , 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[26]  Yong Lian,et al.  A 1-V 60-µW 16-channel interface chip for implantable neural recording , 2009, 2009 IEEE Custom Integrated Circuits Conference.

[27]  Rahul Sarpeshkar,et al.  A Low-Power 32-Channel Digitally Programmable Neural Recording Integrated Circuit , 2011, IEEE Transactions on Biomedical Circuits and Systems.

[28]  Teresa H. Y. Meng,et al.  Adaptive Resolution ADC Array for an Implantable Neural Sensor , 2011, IEEE Transactions on Biomedical Circuits and Systems.

[29]  Franco Maloberti,et al.  A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS , 2010, IEEE Journal of Solid-State Circuits.

[30]  P. Gray,et al.  All-MOS charge redistribution analog-to-digital conversion techniques. I , 1975, IEEE Journal of Solid-State Circuits.