A Low-Cost Test Solution for Reliable Communication in Networks-on-Chip

Networks-on-chip (NoC) provide the communication infrastructure for high-speed and large-scale computation that integrates several IP-cores on a single die. Faults on network channels severely degrade system performance and throughput. This paper presents a distributed and online mechanism for detecting and locating stuck-at faults (SAFs) in NoC channels. We also study the effects of such faults on various network performance metrics. The inherent parallelism present in the architecture is utilized to design a scheduling scheme that reduces the overall test time and overhead significantly. The proposed test solution scales well with network size, channel width, and network topology. Hardware synthesis based on FPGA shows that it needs small area overhead and low test time compared to prior approaches. Furthermore, it improves packet latency and reduces energy consumption.

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