Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm

With the growing complexity of integrated circuits (IC), more and more test patterns are added to test set to test more defects, making the number of test pattern and individual test pattern length continues to increase as the size of IC gets larger, boosting test time and consequently test cost. To solve this problem, this paper proposes a kind of valid pattern identification method. The method uses machine learning to reorder the test pattern which can select the most effective patterns, to determine the optimal training set and test set first. Then, by means of the weighted SVMRANK algorithm to find the optimal pattern sequence. Experiment results demonstrate that the method only sacrifices 2% prediction accuracy in exchange for 3.89 times the time saving. The method aims at maximizing the accuracy of test, and minimizing the number of patterns. The proposed idea significantly improves the test time and test efficiency compared to conventional test flows. This is an innovative test cost reduction method with the growing complexity of IC.

[1]  W. Robert Daasch,et al.  In search of the optimum test set - adaptive test methods for maximum defect coverage and lowest test cost , 2004, 2004 International Conferce on Test.

[2]  R. D. Blanton,et al.  Automated failure population creation for validating integrated circuit diagnosis methods , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[3]  Zhiwei Shao,et al.  Test patterns reordering method based on Gamma distribution , 2020, Integr..

[4]  Edward J. McCluskey,et al.  Gate exhaustive testing , 2005, IEEE International Conference on Test, 2005..

[5]  Terrence Huat Hin Tan,et al.  Adaptive test method on production system-level testing (SLT) to optimize test cost, resources and defect parts per million (DPPM) , 2018, 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

[6]  Nuo Li,et al.  Static Detection of Redundant Test Cases: An Initial Study , 2008, 2008 19th International Symposium on Software Reliability Engineering (ISSRE).

[7]  A. Richard Newton,et al.  Analysis of performance and convergence issues for circuit simulation , 1989 .

[8]  Wojciech Maly,et al.  Fault tuples in diagnosis of deep-submicron circuits , 2002, Proceedings. International Test Conference.

[9]  Edward J. McCluskey,et al.  An experimental chip to evaluate test techniques experiment results , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[10]  Amin Ansari,et al.  Adaptive online testing for efficient hard fault detection , 2009, 2009 IEEE International Conference on Computer Design.

[11]  Jiun-Hsin Liao,et al.  Algorithm based adaptive parametric testing for outlier detection and test time reduction , 2018, 2018 IEEE International Conference on Microelectronic Test Structures (ICMTS).

[12]  Ying Sun,et al.  Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory , 2019, 2019 IEEE 37th VLSI Test Symposium (VTS).

[13]  Edward J. McCluskey,et al.  How Many Test Patterns are Useless? , 2008, 26th IEEE VLSI Test Symposium (vts 2008).

[14]  Haralampos-G. D. Stratigopoulos,et al.  Adaptive Test With Test Escape Estimation for Mixed-Signal ICs , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Irith Pomeranz,et al.  On static test compaction and test pattern ordering for scan designs , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[16]  Kenneth M. Butler,et al.  An empirical study on the effects of test type ordering on overall test efficiency , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[17]  Alex Orailoglu,et al.  Adaptive test optimization through real time learning of test effectiveness , 2011, 2011 Design, Automation & Test in Europe.

[18]  Abhijit Chatterjee,et al.  Adaptive testing of analog/RF circuits using hardware extracted FSM models , 2016, 2016 IEEE 34th VLSI Test Symposium (VTS).

[19]  Peter C. Maxwell.  Adaptive test directions , 2010, 2010 15th IEEE European Test Symposium.

[20]  R. D. Blanton,et al.  Test-set reordering for improving diagnosability , 2017, 2017 IEEE 35th VLSI Test Symposium (VTS).

[21]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[22]  R. D. Blanton,et al.  Diagnosis-Assisted Adaptive Test , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.