Influence of Series Massive Resistance on Capacitance and Conductance Characteristics in Gate-Recessed Nanoscale SOI MOSFETs

Ultrathin body (UTB) and nanoscale body (NSB) SOI MOSFET devices, having a channel thickness ranging from 46 nm (UTB scale) down to 1.6 nm (NSB scale), were fabricated using a selective “gate recessed” process on the same silicon wafer. The gate-to-channel capacitance and conductance complementary characteristics, measured for NSB devices, were found to be radically different from those measured for UTBS. Consistent and trends are observed by varying the frequency , the channel length , and the channel thickness (). In this paper, we show that these trends can be analytically modeled by a massive series resistance depending on the gate voltage and on the channel thickness. The effects of leakage conductance and interface trap density are also modeled. This modeling approach may be useful to analyze and/or simulate electrical behavior of nanodevices in which series resistance is of a great concern.

[1]  P. Balk,et al.  Elimination and Generation of Si ‐ SiO2 Interface Traps by Low Temperature Hydrogen Annealing , 1988 .

[2]  P ? ? ? ? ? ? ? % ? ? ? ? , 1991 .

[3]  J. Chen,et al.  A CV technique for measuring thin SOI film thickness , 1991, IEEE Electron Device Letters.

[4]  G. Ghibaudo,et al.  Mobility Characterization in Advanced FD-SOI CMOS Devices , 2011 .

[5]  Gerard Ghibaudo,et al.  A New Technique to Extract the Source/Drain Series Resistance of MOSFETs , 2009, IEEE Electron Device Letters.

[6]  J. S. Hunter,et al.  Statistics for Experimenters: Design, Innovation, and Discovery , 2006 .

[7]  Chenming Hu,et al.  Threshold voltage and C-V characteristics of SOI MOSFET's related to Si film thickness variation on SIMOX wafers , 1992 .

[8]  Sorin Cristoloveanu,et al.  Experimental determination of short-channel MOSFET parameters , 1985 .

[9]  Characterization of SOI MOSFETs by gate capacitance measurements , 1993, ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures.

[10]  A. Chelly,et al.  Modeling of the Channel Thickness Influence on Electrical Characteristics and Series Resistance in Gate-Recessed Nanoscale SOI MOSFETs , 2013 .

[11]  G. Ghibaudo,et al.  Impact of BOX/substrate interface on low frequency noise in FD-SOI devices , 2007, SPIE International Symposium on Fluctuations and Noise.

[12]  R. F. Motta,et al.  A new method to determine MOSFET channel length , 1980, IEEE Electron Device Letters.

[13]  S. S. Yuen,et al.  Recess channel structure for reducing source/drain series resistance in ultra-thin SOI MOSFETs , 1993, Proceedings of 1993 IEEE International SOI Conference.

[14]  Frédéric Boeuf,et al.  New parameter extraction method based on split C-V for FDSOI MOSFETs , 2012, 2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

[15]  D. Schroder Semiconductor Material and Device Characterization , 1990 .

[16]  B. Aspar,et al.  "Smart cut": a promising new SOI material technology , 1995, 1995 IEEE International SOI Conference Proceedings.

[17]  C. R. Helms,et al.  The Physics and Chemistry of SiO2 and the Si-SiO2 Interface 2 , 1988 .

[18]  G. Ghibaudo,et al.  Characterization and modeling of capacitances in FD-SOI devices , 2011 .

[19]  Jean-Pierre Colinge,et al.  Semiconductor-On-Insulator Materials for Nanoelectronics Applications , 2011 .

[20]  Bich-Yen Nguyen,et al.  Atomic Scale Thickness Control of SOI Wafers for Fully Depleted Applications , 2013 .

[21]  G. Ghibaudo,et al.  Unexpected mobility degradation for very short devices : A new challenge for CMOS scaling , 2006, 2006 International Electron Devices Meeting.