Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip
暂无分享,去创建一个
Thomas J. Snethen | William V. Huott | Peilin Song | Bryan J. Robbins | Mary P. Kusko | Thomas G. Foote | P. Song | Bryan J. Robbins | W. Huott | M. P. Kusko | T. Snethen
[1] B. L. Keller,et al. Built-in self-test support in the IBM engineering design system , 1990 .
[2] Thomas J. Snethen,et al. Advanced microprocessor test strategy and methodology , 1997, IBM J. Res. Dev..
[3] Brion L. Keller,et al. Test methodologies and design automation for IBM ASICs , 1996, IBM J. Res. Dev..
[4] Ion M. Ratiu,et al. Pseudorandom Built-in Self-Test Methodology and Implementation for the IBM RISC System/6000 Processor , 1990, IBM J. Res. Dev..
[5] Brion L. Keller,et al. Delay Test: The Next Frontier for LSSD Test Systems , 1992, Proceedings International Test Conference 1992.
[6] Arvind Srinivasan,et al. Verity - A formal verification program for custom CMOS circuits , 1995, IBM J. Res. Dev..
[7] John A. Waicukauski,et al. A Method for Generating Weighted Random Test Patterns , 1989, IBM J. Res. Dev..
[8] Melvin A. Breuer,et al. Digital Systems Testing and Design for Testability , 1990 .
[9] Paul H. Bardell,et al. Self-Testing of Multichip Logic Modules , 1982, International Test Conference.
[10] Thomas W. Williams,et al. A logic design structure for LSI testability , 1977, DAC '77.
[11] Douglas W. Stout,et al. Boundary-scan design principles for efficient LSSD ASIC testing , 1990 .