A Subthreshold Baseband Processor Core Design With Custom Modules and Cells for Passive RFID Tags

Sophisticated subthreshold passive radio frequency identification tag’s baseband processor (BBP) core design for ultralow-power Internet of Things end devices is presented in this paper. Custom logic cells and tailored logic architectures are applied to eliminate timing violations when the operating voltage is much lower than nominal level. For the consideration of limited availability of radio frequency power, power-aware scheme is applied to the key modules, including PIE decoding and command receiving. Furthermore, Galois linear feedback shift register and double-edge-triggered techniques help to improve clock efficiency and reduce the impact of frequency variation in data link portions. Importantly, a novel custom ratioed logic style is adopted in key modules to fundamentally speed up signals’ propagation at ultralow-voltage. The proposed BBP was fabricated in 90-nm CMOS as well as the regular design with the same function. It was also implemented in the tag chip’s fabrication. In measurement the proposed design indicates good robustness and is much more competent for subthreshold operation. It can operate below 0.3 V with power consumption below 130 nW.