Selective harmonic mitigation technique for multilevel cascaded H-bridge converters

The increasing demand of energy and proliferation of non-linear loads have leaded to the appearance of new grid codes which limit the maximum acceptable harmonic levels. In this context, multilevel topologies are very attractive because can generate output waveforms with a low harmonic content using a low switching frequency. In this paper, the recently presented selective harmonic mitigation technique (SHMPWM) is adapted to a nine-level converter. Its flexibility is exploited to meet the EN 50160 and CIGRE WG 36−05 grid codes without any additional filtering system using 10 switching angles per quarter of period in a wide range of amplitudes of the fundamental harmonic from 0.70 to 1.22. Some results validating this technique applied to this topology are presented. A comparison with the well known selective harmonic elimination method is included showing the advantages of the SHMPWM technique.

[1]  Leopoldo García Franquelo,et al.  A Flexible Selective Harmonic Mitigation Technique to Meet Grid Codes in Three-Level PWM Converters , 2007, IEEE Transactions on Industrial Electronics.

[2]  Huang,et al.  AN EFFICIENT GENERAL COOLING SCHEDULE FOR SIMULATED ANNEALING , 1986 .

[3]  L.G. Franquelo,et al.  The age of multilevel converters arrives , 2008, IEEE Industrial Electronics Magazine.

[4]  Kinattingal Sundareswaran,et al.  Inverter Harmonic Elimination Through a Colony of Continuously Exploring Ants , 2007, IEEE Transactions on Industrial Electronics.

[5]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[6]  T. Lipo,et al.  Hybrid multilevel power conversion system: a competitive solution for high power applications , 1999, Conference Record of the 1999 IEEE Industry Applications Conference. Thirty-Forth IAS Annual Meeting (Cat. No.99CH36370).

[7]  Hui Li,et al.  Optimized PWM strategy based on genetic algorithms , 2005, IEEE Transactions on Industrial Electronics.

[8]  Zhong Du,et al.  Reduced Switching-Frequency Active Harmonic Elimination for Multilevel Converters , 2008, IEEE Transactions on Industrial Electronics.

[9]  V. Agelidis,et al.  Generalized Formulation of Multilevel Selective Harmonic Elimination PWM: Case I -Non-Equal DC Sources , 2006 .

[10]  Leopoldo García Franquelo,et al.  Selective Harmonic Mitigation Technique for High-Power Converters , 2010, IEEE Transactions on Industrial Electronics.

[11]  J.I. Leon,et al.  Implementation of a closed loop SHMPWM technique for three level converters , 2008, 2008 34th Annual Conference of IEEE Industrial Electronics.

[12]  Richard G. Hoft,et al.  Generalized Techniques of Harmonic Elimination and Voltage Control in Thyristor Inverters: Part I--Harmonic Elimination , 1973 .

[13]  Bin Wu,et al.  Multilevel Voltage-Source-Converter Topologies for Industrial Medium-Voltage Drives , 2007, IEEE Transactions on Industrial Electronics.

[14]  Alan J. Watson,et al.  A Complete Harmonic Elimination Approach to DC Link Voltage Balancing for a Cascaded Multilevel Rectifier , 2007, IEEE Transactions on Industrial Electronics.

[15]  Vassilios G. Agelidis,et al.  On Attaining the Multiple Solutions of Selective Harmonic Elimination PWM Three-Level Waveforms Through Function Minimization , 2008, IEEE Transactions on Industrial Electronics.

[16]  Hirofumi Akagi,et al.  A New Neutral-Point-Clamped PWM Inverter , 1981, IEEE Transactions on Industry Applications.

[17]  Mariusz Malinowski,et al.  Comparison of 2.3-kV Medium-Voltage Multilevel Converters for Industrial Medium-Voltage Drives , 2007, IEEE Transactions on Industrial Electronics.

[18]  Kay Soon Low,et al.  A Multiobjective Genetic Algorithm for Optimizing the Performance of Hard Disk Drive Motion Control System , 2007, IEEE Transactions on Industrial Electronics.

[19]  Tian-Hua Liu,et al.  Optimum harmonic reduction with a wide range of modulation indexes for multilevel converters , 2002, IEEE Trans. Ind. Electron..