The application of a novel direct digital frequency synthesizer for the IP core design of all digital three phase SPWM generator

This work presents a novel method based on direct digital frequency synthesizer (DDS or DDFS) for all digital three phase SPWM generator IP core, which is improved from conventional DDS method. This method changes the frequency of the sine wave by changing the clock of taking the sample data while the number of the sample data in every period is constant, which eliminates the problem of the precision of the sine wave. In addition, the ROM size to store the sample data of sine wave is reduced to one fourths of conventional one by adding an up/down address counter between numerically controlled oscillator (NCO) and sinusoidal look-up table. Finally the simulation results with EDA tool-CANDENCE NC/spl I.bar/verilog are presented and the simulation results prove the design is reasonable.

[1]  D. Al-Khalili,et al.  ROM size reduction with low processing cost for direct digital frequency synthesis , 2001, 2001 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (IEEE Cat. No.01CH37233).

[2]  J. Vankka.  Methods of mapping from phase to sine amplitude in direct digital synthesis , 1997, IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control.

[3]  Dhamin Al-Khalili,et al.  A low power direct digital frequency synthesizer with 60 dBc spectral purity , 2002, GLSVLSI '02.

[4]  Daniel Y. Abramovitch,et al.  Phase-locked loops: a control centric tutorial , 2002, Proceedings of the 2002 American Control Conference (IEEE Cat. No.CH37301).