A Generic Scalable Architecture for Min-Sum/Offset-Min-Sum Unit for Irregular/Regular LDPC Decoder

The most common algorithm used in iterative decoding of low-density parity check (LDPC) codes is based on a generic class of the sum-product algorithm, which has a nonlinear dependence on the log(tanh()) function. The implementation based on fixed precision has substantial loss of accuracy and is computationally expensive with full precision. A suboptimal version of belief propagation called the <i>offset-min-sum</i> algorithm is generally used in hardware implementation. This paper proposes a generic scalable architecture for minimum search during check-node operation in the <i>offset-min-sum</i> algorithm applicable to regular as well as irregular LDPC codes with check node of any degree <i>d</i>. For an LDPC code with maximum check node degree <i>d</i>, the proposed architecture consists of 2(<i>d</i>-2) 2 × 1 multiplexers and 3(<i>d</i>-2) two-input compare-and-select units (CSUs). This has latency of [2⌈log₂(<i>d</i>)⌉-2]<i>tdc</i> when ⌈log₂(<i>d</i>)⌉-log₂(<i>d</i>) <; log₂(4/3) else [2⌈log₂(<i>d</i>)⌉-3]<i>tdc</i>, with <i>tdc</i> representing the delay of a two-input CSU. The proposed architecture has been implemented for <i>d</i> = 20 using a TSMC 0.18-μm CMOS process.