Capture-power-aware test data compression using selective encoding

Ever-increasing test data volume and excessive test power are two of the main concerns of VLSI testing. The ''don't-care'' bits (also known as X-bits) in given test cube can be exploited for test data compression and/or test power reduction, and these techniques may contradict to each other because the very same X-bits are likely to be used for different optimization objectives. This paper proposes a capture-power-aware test compression scheme that is able to keep capture-power under a safe limit with low test compression ratio loss. Experimental results on benchmark circuits validate the effectiveness of the proposed solution.

[1]  Kozo Kinoshita,et al.  Low-capture-power test generation for scan-based at-speed testing , 2005, IEEE International Conference on Test, 2005..

[2]  Krishnendu Chakrabarty,et al.  Test data compression for IP embedded cores using selective encoding of scan slices , 2005, IEEE International Conference on Test, 2005..

[3]  Alex Orailoglu,et al.  Reducing test application time through test data mutation encoding , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[4]  Krishnendu Chakrabarty,et al.  Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes , 2003, IEEE Trans. Computers.

[5]  Sybille Hellebrand,et al.  Data compression for multiple scan chains using dictionaries with corrections , 2004, 2004 International Conferce on Test.

[6]  Qiang Xu,et al.  A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[7]  Erik H. Volkerink,et al.  Efficient seed utilization for reseeding based compression [logic testing] , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[8]  Irith Pomeranz,et al.  Low Shift and Capture Power Scan Tests , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

[9]  Brion L. Keller,et al.  A SmartBIST variant with guaranteed encoding , 2001, Proceedings 10th Asian Test Symposium.

[10]  Bashir M. Al-Hashimi,et al.  Variable-length input Huffman coding for system-on-a-chip test , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Krishnendu Chakrabarty,et al.  Reduction of SOC test data volume, scan power and testing time using alternating run-length codes , 2002, DAC '02.

[12]  Bashir M. Al-Hashimi,et al.  Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  B. Koneman,et al.  LFSR-Coded Test Patterns for Scan Designs , 1993 .

[14]  Janusz Rajski,et al.  Ring generators - new devices for embedded test applications , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Daniel G. Schweikert,et al.  Proceedings of the 29th ACM/IEEE Design Automation Conference , 1992, DAC 1992.

[16]  Nur A. Touba,et al.  Test vector encoding using partial LFSR reseeding , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[17]  Janak H. Patel,et al.  Reducing test application time for full scan embedded cores , 1999, Digest of Papers. Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing (Cat. No.99CB36352).

[18]  Nilanjan Mukherjee,et al.  Embedded deterministic test , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  Kuen-Jong Lee,et al.  Using a single input to support multiple scan chains , 1998, ICCAD '98.

[20]  徐强.  Capture-Power-Aware Test Data Compression Using Selective Encoding , 2011 .

[21]  Nur A. Touba,et al.  Adjustable Width Linear Combinational Scan Vector Decompression , 2003, ICCAD.

[22]  Xiaowei Li,et al.  A Scan Chain Adjustment Technology for Test Power Reduction , 2006, 2006 15th Asian Test Symposium.

[23]  Irith Pomeranz,et al.  On test data volume reduction for multiple scan chain designs , 2003, TODE.

[24]  Kenneth M. Butler,et al.  A case study of ir-drop in structured at-speed testing , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[25]  Alex Orailoglu,et al.  Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs , 2003, IEEE Trans. Computers.

[26]  Nur A. Touba,et al.  An efficient test vector compression scheme using selective Huffman coding , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[27]  Krishnendu Chakrabarty,et al.  System-on-a-chip test-data compression and decompressionarchitectures based on Golomb codes , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[28]  Patrick Girard,et al.  Efficient scan chain design for power minimization during scan testing under routing constraint , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[29]  Subhasish Mitra,et al.  Efficient Seed Utilization for Reseeding based Compression , 2003 .

[30]  Nur A. Touba,et al.  Test vector decompression via cyclical scan chains and its application to testing core-based designs , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[31]  Xiaoqing Wen,et al.  Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing , 2008, 2008 IEEE International Test Conference.

[32]  João Paulo Teixeira,et al.  Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors , 2011, 29th VLSI Test Symposium.

[33]  Lee Whetsel,et al.  Adapting scan architectures for low power operation , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[34]  Nur A. Touba,et al.  Test data compression using dictionaries with selective entries and fixed-length indices , 2003, TODE.

[35]  A. Arulmurugan,et al.  Survey of low power testing of VLSI circuits , 2012, 2012 International Conference on Computer Communication and Informatics.

[36]  Nur A. Touba,et al.  Survey of Test Vector Compression Techniques , 2006, IEEE Design & Test of Computers.

[37]  Nur A. Touba,et al.  Reducing power dissipation during test using scan chain disable , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[38]  P. Girard,et al.  Power-Aware Test Data Compression for Embedded IP Cores , 2006, 2006 15th Asian Test Symposium.

[39]  Irith Pomeranz,et al.  Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs , 2006, 2006 IEEE International Test Conference.

[40]  Qiang Xu,et al.  Pattern-directed circuit virtual partitioning for test power reduction , 2007, 2007 IEEE International Test Conference.

[41]  Xiaoqing Wen,et al.  A Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation , 2006, 2006 International Conference on Computer Design.

[42]  R. Nelson.  The last byte - Yet another thiotimoline application , 2002, IEEE Design & Test of Computers.

[43]  Yu Hu,et al.  iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing , 2008, 2008 Design, Automation and Test in Europe.

[44]  Subhasish Mitra,et al.  XPAND: an efficient test stimulus compression technique , 2006, IEEE Transactions on Computers.

[45]  Minesh B. Amin,et al.  Efficient compression and application of deterministic patterns in a logic BIST architecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).