Design of a weighted fair queueing cell scheduler for ATM networks

Today, ATM networks are being used to carry bursty data traffic with large and highly variable rates, and burst sizes ranging from kilobytes to megabytes. Obtaining good statistical multiplexing performance for this kind of traffic requires much larger buffers than are needed for more predictable applications or for bursty data applications with more limited burst transmission rates. Large buffers lead to large queueing delays, making it necessary for switches to implement more sophisticated queueing mechanisms in order to deliver acceptable quality of service (QoS). This paper describes a 2.4 Gb/ s ATM queue management chip that has practically unlimited buffer scaling and which supports dynamic per VC queueing, an efficiently implementable form of weighted fair queueing, a novel packet-level discarding algorithm and the ability to support multiple output links. We give a detailed description of our weighted fair queueing scheduling method, which we call the binary scheduling wheels (BSW) algorithm. The BSW algorithm smooths bursty traffic and guarantees minimum transmission rates during overload. The BSW algorithm uses a binary counter based scheduling mechanism and is well-suited to hardware implementation.