Simulation ofswitching noiseinon-chip powerdistribution networks ofFPGAs

Anexplicit approach hasbeenusedtosimulate switching noise inon-chip powerdistribution networks. This approach hasbeenextended toanalyze on-chip powerdistribution networks ofFieldProgrammable GateArray (FPGA), whosepowerdistribution network ismoreirregular thanthatofanApplication Specific Integrated Circuit (ASIC). Theswitching noise hasbeencompared between theon-chip powerdistribution networks ofFPGAsand ASICs. Switching noise simulation ofpower/ground grids requires astatic IRdropanalysis before thetransient simulation. Theimportance ofperforming a static IRdropanalysis prior tothetransient simulation hasbeen illustrated. 1.Introduction Simulation andanalysis ofsimultaneous switching noise inon-chip powerdistribution networks (PDN)isimportant for designing high-performance systems. Theon-chip PDNsofApplication-Specific Integrated Circuit (ASIC) areusually the focus ofswitching noise simulation owingtotheir highclock frequencies. Thepower/ground lines inthese PDNsusually haveuniform cross-section andrunfromoneside ofthechiptotheother. Suchsimple PDN structures makesimulation of switching noise inthemalittle easier. Field Programmable GateArrays (FPGA)share almost alltheproperties ofanASICbarring theclock frequency, which forFPGAsisapproximately one-tenth oftheASIC's clock frequency. Duetotheincreased circuit density, anddecreasing voltage levels inFPGAs,switching noise analysis forsuchsystems becomes important. Iftheclock frequency ofFPGAs increases inthefuture, thenswitching noise analysis will beessential forthem. Unlike theon-chip PDNsoftheASICs, the on-chip PDNsofFPGAsarenotsimple. Thepower/ground lines maybediscontinuous. Thatis, thelines donotrunfromone side ofthechiptotheother. A line running fromoneside toother side ofthechip maycontain pieces oflines ofvarying widths. Thismakesthepower/ground lines tohavenon-uniform cross-sections. Suchcomplicated PDNsmaketheswitching noise simulation inthemachallenge. Inthis paper, switching noise is simulated foraon-chip PDNgeometry typical ofFPGAs. Switching noise simulation hasthefollowing twosteps: 1)Static W V-V4