论文信息 - DFT techniques for memory macro with built-in ECC

DFT techniques for memory macro with built-in ECC

DFT techniques to implement ECC circuitry on memory macro with no additional test cost are proposed. New methodology to design a Hamming code matrix is used to achieve whole ECC system testing with standard memory BIST and conventional test sequence. The proposed ECC techniques are implemented in a 512Kb SRAM macro and demonstrated by hardware characterization with 90nm technology.

Osamu Hirabayashi | Yasuhisa Takeyama | Keiichi Kushida | Nobuaki Otsuka

[1] Kewal K. Saluja,et al. Testing check bits at no cost in RAMs with on-chip ECC , 1993 .

[2] Parameswaran Ramanathan,et al. Zero cost testing of check bits in RAMs with on-chip ECC , 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.

[3] Cristina Silvano,et al. VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes , 1995, Proceedings of the 8th International Conference on VLSI Design.