Summary form only given, as follows. The SIA National Technology Roadmap and Ivloore?s Law both predict that logic chips containing one billion transistors will ship by the year 2010. This panel will explore the challenges awaiting the CAD industry as we move toward such huge chip:;. These chips will almost certainly include a variety of technologies, including logic, microprocessor cores, buses, static and dynamic memory, analog circuitry, and possibly micromechanical devices. Challenges loom at all levels of system abstraction, from artwork to architecture, and all aspects of CAD, from data management to algorithms. The panelists, whose expertise ranges from interconnect and noise through system-level synthesis, will begin by summarizing these CAD challenges and identifying key areas where contributions are needed, and then discuss promising research directions.