Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard
暂无分享,去创建一个
[1] Adi Shamir,et al. A method for obtaining digital signatures and public-key cryptosystems , 1978, CACM.
[2] Michel Renovell,et al. Scan Design and Secure Chip , 2004, IOLTS.
[3] Wolfgang Fichtner,et al. A 177 Mb/s VLSI implementation of the International Data Encryption Algorithm , 1994 .
[4] Patrick Schaumont,et al. Design and performance testing of a 2.29-GB/s Rijndael processor , 2003, IEEE J. Solid State Circuits.
[5] Edward W. Chencinski,et al. S/390 Parallel Enterprise Server CMOS Cryptographic Coprocessor , 1999, IBM J. Res. Dev..
[6] Ramesh Karri,et al. Scan based side channel attack on dedicated hardware implementations of Data Encryption Standard , 2004 .
[7] M. Renovell,et al. Scan design and secure chip [secure IC testing] , 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.
[8] Ramesh Karri,et al. Secure scan: a design-for-test architecture for crypto chips , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[9] Mark Mohammad Tehranipoor,et al. Securing Scan Design Using Lock and Key Technique , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).
[10] Ingrid Verbauwhede,et al. A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology , 2005, ACM Great Lakes Symposium on VLSI.
[11] Maciej Nikodem,et al. Low-cost and Universal Secure Scan: a Design- Architecture for Crypto Chips , 2006, 2006 International Conference on Dependability of Computer Systems.
[12] Trevor Mudge,et al. A 2.3Gb/s fully integrated and synthesizable AES Rijndael core , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..
[13] Wolfgang Fichtner,et al. VINCI: Secure test of a VLSI high-speed encryption system , 1993, Proceedings of IEEE International Test Conference - (ITC).
[14] Sandra Dominikus,et al. A Highly Regular and Scalable AES Hardware Architecture , 2003, IEEE Trans. Computers.