Data driven power optimization of sequential circuits

In this paper we present an efficient technique to reduce the power dissipation in a technology mapped CMOS sequential circuit based on logic and structural transformations. The power reduction is achieved by adding sequential redundancies from low switching activity gates to high switching activity gates (targets) such that the switching activities at the output of the targets are significantly reduced. We show that the power reducing transformations result in a circuit that is a valid replacement of the original. The notion of validity used here is that of a delay safe replacement. The potential transformations are found by direct logic implications applied to the circuit netlist. Therefore the complexity of the proposed transformation is polynomial in the size of the circuit, allowing the processing of large designs.

[1]  Dhiraj K. Pradhan,et al.  Gate-level synthesis for low-power using new transformations , 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

[2]  Robert K. Brayton,et al.  Multi-Level Synthesis For Safe Replaceability , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[3]  Melvin A. Breuer,et al.  On Redundancy and Fault Detection in Sequential Circuits , 1979, IEEE Transactions on Computers.

[4]  David E. Long,et al.  Surprises in sequential redundancy identification , 1996, Proceedings ED&TC European Design and Test Conference.

[5]  B. Wurth,et al.  Reducing power dissipation after technology mapping by structural transformations , 1996, 33rd Design Automation Conference Proceedings, 1996.

[6]  Enrico Macii,et al.  Symbolic computation of logic implications for technology-dependent low-power synthesis , 1996, ISLPED '96.

[7]  Kwang-Ting Cheng,et al.  Sequential logic optimization by redundancy addition and removal , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[8]  D. E. Long,et al.  Identifying sequential redundancies without search , 1996, 33rd Design Automation Conference Proceedings, 1996.

[9]  Sarma Vrudhula,et al.  Multi-level logic optimization for low power using local logic transformations , 1996, ICCAD 1996.

[10]  Enrico Macii,et al.  Symbolic computation of logic implications for technology-dependent low-power synthesis , 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

[11]  Srinivas Devadas,et al.  Retiming sequential circuits for low power , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[12]  Robert K. Brayton,et al.  Exploiting power-up delay for sequential optimization , 1995, Proceedings of EURO-DAC. European Design Automation Conference.

[13]  Carl Pixley,et al.  The Verifiacation Problem for Safe Replaceability , 1994, CAV.

[14]  Massoud Pedram,et al.  Multi-level Network Optimization For Low Power , 1994, IEEE/ACM International Conference on Computer-Aided Design.