A 70 ns high density 64K CMOS dynamic RAM

A 64K /spl times/ 1 CMOS dynamic RAM has been developed in a double-poly n-well CMOS technology with device scaling to the HMOS III level. A p-channel memory array with n-well protection reduced the operating soft error rate to less than one FIT. Periphery complexity is simplified due to CMOS circuits resulting in a size of 30,464 mil/SUP 2/ with a redundancy efficiency of 68%. The RAM has a typical access time of 70 ns and a CMOS standby power of 25 /spl mu/W. In addition, a static column design offers 35-ns data cycle time for high-bandwidth application.

[1]  Y. Kamigaki,et al.  An n-Well CMOS Dynamic RAM , 1982, IEEE Journal of Solid-State Circuits.

[2]  M. T. Bohr,et al.  HMOS-CMOS-a low-power high-performance technology , 1981 .

[3]  H. Masuda,et al.  An n-well CMOS dynamic RAM , 1982, IEEE Transactions on Electron Devices.

[4]  K. Shirai,et al.  A 150ns 288k CMOS EPROM with redundancy , 1983, 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[5]  T. Masuhara,et al.  A Hi-CMOSII 8Kx8 bit static RAM , 1982, IEEE Journal of Solid-State Circuits.

[6]  H. Shinohara,et al.  A 64Kb full CMOS RAM with divided word line structure , 1983, 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.