Automatic Identification of Yield Limiting Layout Patterns Using Root Cause Deconvolution on Volume Scan Diagnosis Data

in many cases, the main cause of yield loss is a specific layout pattern that is difficult to manufacture and is prone to causing an open or short defect. This situation is getting worse with advanced technology nodes due to small feature sizes and complex manufacturing processes. Volume scan diagnosis results are a rich data source for identifying such yield limiting layout patterns, but a big challenge is how to deal with an enormously large number of potential layout patterns to be considered for analysis and how to avoid over fitting. In this paper we present enhancements to the previously published root cause deconvolution technique for analyzing volume scan diagnosis data that enables it to overcome this and correctly, and automatically, determine the right layout patterns causing systematic yield loss. Also presented is an application to industrial data where a layout pattern identified by the new technique was validated by physical root cause analysis to be the dominant yield loss mechanism.

[1]  Cédric du Mouza,et al.  SD-Rtree: A Scalable Distributed Rtree , 2007, 2007 IEEE 23rd International Conference on Data Engineering.

[2]  Enamul Amyeen,et al.  Improving Precision Using Mixed-level Fault Diagnosis , 2006, 2006 IEEE International Test Conference.

[3]  Janusz Rajski,et al.  A Rapid Yield Learning Flow Based on Production Integrated Layout-Aware Diagnosis , 2006, 2006 IEEE International Test Conference.

[4]  Atul Chittora.  Leveraging Root Cause Deconvolution Analysis for Logic Yield Ramping , 2013 .

[5]  G. McLachlan,et al.  The EM algorithm and extensions , 1996 .

[6]  Darrell Carder,et al.  High-Volume Scan Analysis: Practical challenges and applications for industrial IC development , 2010, 2010 IEEE International Test Conference.

[7]  Wojciech Maly,et al.  Fault tuples in diagnosis of deep-submicron circuits , 2002, Proceedings. International Test Conference.

[8]  Rao Desineni,et al.  Hard to find, easy to find systematics; just find them , 2010, 2010 IEEE International Test Conference.

[9]  Julie Lee,et al.  Identifying design systematics using learning based diagnostic analysis , 2010, 2010 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC).

[10]  Franz Aurenhammer,et al.  A Novel Type of Skeleton for Polygons , 1996 .

[11]  Wu-Tung Cheng,et al.  Efficiently Performing Yield Enhancements by Identifying Dominant Physical Root Cause from Test Fail Data , 2008, 2008 IEEE International Test Conference.

[12]  R. D. Blanton,et al.  Systematic defect identification through layout snippet clustering , 2010, 2010 IEEE International Test Conference.

[13]  R. D. Blanton,et al.  LASIC: Layout Analysis for Systematic IC-Defect Identification Using Clustering , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  R. D. Blanton,et al.  Physically-aware analysis of systematic defects in integrated circuits , 2011, 2011 IEEE International Test Conference.

[15]  Chan Huan Gim.  A novel bitmap analysis technique - test sensitivity intensity bitmap , 2002, Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614).

[16]  Friedrich Hapke,et al.  Diagnosing Cell Internal Defects Using Analog Simulation-Based Fault Models , 2014, 2014 IEEE 23rd Asian Test Symposium.

[17]  R. D. Blanton,et al.  A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect Behavior , 2006, 2006 IEEE International Test Conference.

[18]  Sudhakar M. Reddy,et al.  Faster defect localization in nanometer technology based on defective cell diagnosis , 2007, 2007 IEEE International Test Conference.

[19]  T. Herrmann,et al.  Identifying systematic critical features using silicon diagnosis data , 2012, 2012 SEMI Advanced Semiconductor Manufacturing Conference.

[20]  Thomas Herrmann,et al.  Determining a Failure Root Cause Distribution From a Population of Layout-Aware Scan Diagnosis Results , 2012, IEEE Design & Test of Computers.

[21]  Manish Sharma,et al.  Layout-aware Diagnosis Leads to Efficient and Effective Physical Failure Analysis , 2011 .

[22]  Sudhakar M. Reddy,et al.  Diagnosis of Cell Internal Defects with Multi-cycle Test Patterns , 2012, 2012 IEEE 21st Asian Test Symposium.

[23]  Yici Cai,et al.  Efficient Process-Hotspot Detection Using Range Pattern Matching , 2006, IEEE/ACM International Conference on Computer-Aided Design.

[24]  Friedrich Hapke,et al.  Cell-aware Production test results from a 32-nm notebook processor , 2012, 2012 IEEE International Test Conference.