A 320MHz–2.56GHz low jitter phase-locked loop with adaptive-bandwidth technique
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[1] Zhongyuan Chang,et al. A self-biased PLL with current-mode filter for clock generation , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
[2] Longsheng Wu,et al. Short locking time Phase-Locked Loop based on adaptive bandwidth control , 2010, 2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC).
[3] Jihyun Kim,et al. A 1.2mW 0.02mm2 2GHz Current-Controlled PLL Based on a Self-Biased Voltage-to-Current Converter , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[4] J.G. Maneatis,et al. Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
[5] Chih-Kong Ken Yang,et al. A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation , 2003 .
[6] Jaeha Kim,et al. Design of CMOS adaptive-bandwidth PLL/DLLs: a general approach , 2003, IEEE Trans. Circuits Syst. II Express Briefs.
[7] M. Horowitz,et al. Precise delay generation using coupled oscillators , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[8] Jaeha Kim,et al. Self-biased, high-bandwidth, low-jitter 1-to-4096 multiplier clock-generator PLL , 2003 .
[9] Ian A. Young,et al. A scalable sub-1.2mW 300MHz-to-1.5GHz host-clock PLL for system-on-chip in 32nm CMOS , 2011, 2011 IEEE International Solid-State Circuits Conference.
[10] M. Horowitz,et al. Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).
[11] Hao Yu,et al. A Dividerless PLL With Low Power and Low Reference Spur by Aperture-Phase Detector and Phase-to-Analog Converter , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.
[12] Jin-Sheng Wang,et al. A PVT tolerant 0.18MHz to 600MHz self-calibrated digital PLL in 90nm CMOS process , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
[13] A.M. Fahim. A compact, low-power low-jitter digital PLL , 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).
[14] Bishop Brock,et al. A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling , 2002, IEEE J. Solid State Circuits.