VLSI architecture for H.264 integer-pel motion estimation with minimum memory bandwidth requirement

A novel memory-access and computation efficient full-search verylarge-scale integrated-circuit(VLSI) architecture for H.264/AVC integer-pel motion estimation was proposed.With the highest level of on-chip data reuse,one-access for off-chip reference pixels was achieved,and the memory bandwidth requirement was minimized.By distributed data caching and imaginary connection of picture boundaries,the memory access of reference pixels was regular and efficient.Simple processing elements were systolically connected,and worked in single-instruction multiple-data(SIMD) manner,with 100% utilization.The proposed architecture fully supports variable block-size matching of H.264/AVC,and can produce 41 sums of absolute difference(SAD) for one search point every cycle without bubble.The architecture was described in parameterized design.For standard definition digital television(SDTV) applications,an implementation was accomplished based on the Faraday 0.18 μm CMOS standard cell technology,with 151×103 logic gates,3.86 ns critical path delay,23.75 kB on-chip memory,and 8 bit data I/O pins.Working at 216 MHz clock frequency,the implementation could support realtime SDTV 720×576@30fps,with the search range of [-32,32]×[-16,16],2 reference pictures,and 24.9 MB/s off-chip memory bandwidth.