论文信息 - Challenges raised by long on-chip wiring for CMOS microprocessor applications

Challenges raised by long on-chip wiring for CMOS microprocessor applications

The unique characteristics of long on-chip interconnections in terms of modelling, simulation and design practices are investigated for representative five-layer structures. Experimental results are shown for a specially designed test vehicle with lines as long as 1.6 cm and line resistance of R=35 to 500 /spl Omega//cm.

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