Critical Issues Regarding the Trace Cache Fetch Mechanism

In order to meet the demands of wider issue processors, fetch mechanisms will need to fetch multiple basic blocks per cycle. The trace cache supplies several basic blocks each cycle by storing logically contiguous instructions in physically contiguous storage. When a particular basic block is requested, the trace cache can potentially respond with the requested block along with several blocks that followed it when the block was last encountered. In this technical report, we examine some critical features of a trace cache mechanism designed for a 16-wide issue processor and evaluate their eeects on performance. We examine features such as cache associativity, storage partitioning, branch predictor design, instruction cache design, and ll unit design. We compare the performance of our trace cache mechanism with that of the design presented by Rotenberg et al 19] and show a 23% improvement in performance. In our nal analysis, we compare our trace cache mechanism with an aggressive single basic block fetch mechanism and show that the trace cache mechanism attains a 24% improvement in performance.

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