Trade-Off Analysis of a Low-Power Image Coding Algorithm

In this paper, a novel algorithm for low-power image coding and decoding is presented and the various inherent trade-offs are described and investigated in detail. The algorithm reduces the memory requirements of vector quantization, i.e., the size of memory required for the codebook and the number of memory accesses by using small codebooks. This significantly reduces the memory-related power consumption, which is an important part of the total power budget. To compensate for the loss of quality introduced by the small codebook size, simple transformations are applied on the codewords during coding. Thus, small codebooks are extended through computations and the main coding task becomes computation-based rather than memory-based. Each image block is encoded by a codeword index and a set of transformation parameters. The algorithm leads to power savings of a factor of 10 in coding and of a factor of 3 in decoding, at least in comparison to classical full-search vector quantization. In terms of SNR, the image quality is better than or comparable to that corresponding to full-search vector quantization, depending on the size of the codebook that is used. The main disadvantage of the proposed algorithm is the decrease of the compression ratio in comparison to vector quantization. The trade-off between image quality and power consumption is dominant in this algorithm and is mainly determined by the size of the codebook.

[1]  Anantha P. Chandrakasan,et al.  Low Power Digital CMOS Design , 1995 .

[2]  Allen Gersho,et al.  Vector quantization and signal compression , 1991, The Kluwer international series in engineering and computer science.

[3]  A. Jacquin.  Fractal image coding: a review , 1993, Proc. IEEE.

[4]  Roberto Guerrieri,et al.  A 2D-DCT low-power architecture for H.261 coders , 1995, 1995 International Conference on Acoustics, Speech, and Signal Processing.

[5]  Arnaud E. Jacquin,et al.  Image coding based on a fractal theory of iterated contractive image transformations , 1992, IEEE Trans. Image Process..

[6]  Jan M. Rabaey,et al.  Architectural power analysis: The dual bit type method , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[7]  Yu Hen Hu.  Optimal VLSI architecture for vector quantization , 1995, 1995 International Conference on Acoustics, Speech, and Signal Processing.

[8]  John P. Knight,et al.  Optimizing Power in ASIC Behavioral Synthesis , 1996, IEEE Des. Test Comput..

[9]  H. De Man,et al.  Optimization of memory organization and hierarchy for decreased size and power in video and image processing systems , 1995, Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing.

[10]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[11]  Robert M. Gray,et al.  An Algorithm for Vector Quantizer Design , 1980, IEEE Trans. Commun..

[12]  Jan M. Rabaey,et al.  An Integrated CAD Environment for Low-Power Design , 1996, IEEE Des. Test Comput..

[13]  Lyman P. Hurd,et al.  Fractal image compression , 1993 .

[14]  Massoud Pedram,et al.  Low power design methodologies , 1996 .

[15]  Roberto Guerrieri,et al.  A block-matching module for video compression , 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.

[16]  Teresa H. Meng,et al.  Video compression for portable communication using pyramid vector quantization of subband coefficients , 1993, Proceedings of IEEE Workshop on VLSI Signal Processing.

[17]  Hugo De Man,et al.  Global Communication and Memory Optimizing Transformations for Low Power Systems , 1994 .

[18]  Jan M. Rabaey.  Exploring the Power Dimension , 1996 .

[19]  Jan M. Rabaey,et al.  Early power exploration—a World Wide Web application , 1996, DAC '96.

[20]  Jan M. Rabaey,et al.  Design guidance in the power dimension , 1995, 1995 International Conference on Acoustics, Speech, and Signal Processing.

[21]  Anantha P. Chandrakasan,et al.  A low-power chipset for a portable multimedia I/O terminal , 1994 .

[22]  K. J. Ray Liu,et al.  A low-power and low-complexity DCT/IDCT VLSI architecture based on backward Chebyshev recursion , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[23]  Jan M. Rabaey.  Exploring the power dimension [in digital CMOS] , 1996, Proceedings of Custom Integrated Circuits Conference.