论文信息 - A re-engineering approach to low power FPGA design using SPFD

A re-engineering approach to low power FPGA design using SPFD

In this paper, we present a method to re-synthesize Look-Up Table (LUT) based Field Programmable Gate Arrays (FPGAs) for low power design after technology mapping, placement and routing are performed. We use Set of Pairs of Functions to be Distinguished (SPFD) to express functional permissibility of each signal. Using different propagations of SPFD to fan-in signals, we change the functionality of a PLB (Programmable Logic Block) which drives large loading into one with low transition density. Experimental results show that our method can reduce on average 12% power consumption compared to the original circuits without affecting placement and routing.

TingTing Hwang | Jan-Min Hwang | Feng-Yi Chiang

[1] Marios C. Papaefthymiou,et al. Precomputation-based sequential logic optimization for low power , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[2] Marios C. Papaefthymiou,et al. Precomputation-based sequential logic optimization for low power , 1994, ICCAD '94.

[3] Hiroshi Sawada,et al. A new method to express functional permissibilities for LUT based FPGAs and its applications , 1996, ICCAD 1996.

[4] Sharad Malik,et al. Technology Mapping for Low Power , 1993, 30th ACM/IEEE Design Automation Conference.

[5] Chau-Shen Chen,et al. Low power FPGA design—a re-engineering approach , 1997, DAC.

[6] Pierre Marchal,et al. Field-programmable gate arrays , 1999, CACM.

[7] Hiroshi Sawada,et al. A new method to express functional permissibilities for LUT based FPGAs and its applications , 1996, Proceedings of International Conference on Computer Aided Design.