HIGH EFFICIENT CLUSTERING OF TARGET FFs FOR LACG

In VLSI design, low power consumption is most important parameter. Low power is achieved through power gating and clock gating methods. Power gating is used for static power reduction. Clock gating is used for dynamic power reduction. Dynamic power refers to the power consumed by operating terminals. Cluster target flip flops and the gating signal to those flip-flops should be provided by common gating circuit, so the unwanted power consumed by separate gating circuit for each target flip-flop has been reduced, this leads to low power consumption. Clock gating technique is well known to reduce the power consumed by the clock signals in the system. With clock gating, the clock signals are AND'ed with explicitly predefined enabling signals. Clock gating is employed at all levels: system architecture, block design, logic design and gates, toggling probability. In this paper, we design and implement the new concept of Target Flip Flop's which are cluster to make an efficient Look Ahead Carry Generator's. By developing a probabilistic model of the clock gating network, the expected power savings and the implied overhead are quantified. Expressions for the power savings in a gated clock tree are presented and the optimal gater fan-out is derived, based on flip-flops toggling probabilities and process technology parameters. The resulting clock gating methodology achieves 10% savings of the total clock tree switching power. Clock gating does not come for free. Extra logic and interconnects are required to generate the clock enabling signals and the resulting area and power overheads must be considered. In the extreme case, each clock input of a FF can be disabled individually, yielding maximum clock suppression.